1. Field of the Invention
The present invention relates in general to an asynchronous transfer mode (referred to hereinafter as ATM) multiplexing system which can be commonly used in ATM network nodes, network termination units, terminal interface units and etc. as parts of a broadband integrated services digital network (referred to hereinafter as B-ISDN). More particularly, the present invention relates to an ATM statistical multiplexing system having a priority processing function and an ATM header changing function which are performed on the basis of buffer storage level information and link service priority information at input stages.
2. Description of the Prior Art
Various high quality services have been required by subscribers with the communication techniques already developed. According to such a trend, an ATM B-ISDN has been introduced to provide a consecutive service, such as a voice service, a high speed data service, such as a file transmission service and a burst-type service, such as a variable bit rate (referred to hereinafter as VBR) real time video service on the same transmission link. A multiplexing system suitable for such an environment is a kernel of a telecommunication system, and is used in a time division multiplexing (referred to hereinafter as TDM) circuit for-an optical cable and in a cross pointer switch. Several methods have been proposed to implement such a multiplexing system. However, a proposed TDM system is suitable for an existing STM. For this reason, there is a necessity for implementing a flexible multiplexing system suitable for the future-oriented ATM B-ISDN.
An ATM statistical multiplexing system is a flexible network transfer technique which is capable of processing burst-type traffic as well as consecutive traffic. In particular, in view of data transmission, the ATM statistical multiplexing system has a flexible asynchronous multi-transmission function which is capable of processing a high speed data service in 150 Mbps class and a consecutive stream of data at a lower speed. In the STM network, a desired bandwidth on a trunk can be obtained by mathematically summing all fixed bit rates. But, the ATM network is increased in efficiency by a statistical multiplexing effect on sources under the condition that the sources are sufficiently multiplexed and are of no relevance to one another.
A broadband terminal adapter is required to multiplex various service links into a single cell stream based on a link service priority. Also, in a broadband network termination unit (B-NT2), a user network interface (referred to hereinafter as UNI) is required to concentration-multiplex cells sent from a plurality of subscriber transmission lines into a single consecutive cell stream to satisfy characteristics of services belonging to the cells. These ATM multiplexing functions are important parts for the implementation of the B-ISDN. The ATM multiplexing system must reflect a network-in-flexibility for the purpose of an increase in application to various services and of the optimum use of available resources. Also, the ATM multiplexing system must accommodate services and the associated terminals independent of a network clock for the purpose of coupling a plurality of sources in the ATM network on a single transmission link. These characteristics result in cell loss and cell delay displacement in the ATM multiplexing.
For this reason, the ATM multiplexing system must have input stages with such a construction as to accommodate various services independent of a network clock. Also, the ATM multiplexing system must perform a flexible cell process based on a priority of various service links. Basically, a plurality of inputs must be routed to a single output with no cell conflict and, at the same time, a changed header must be transferred. To this end, the fastest device technique must be used to implement such an ATM multiplexing system.
Referring to FIG. 1A, there is shown a block diagram of a conventional ATM multiplexing system. Basically, the conventional ATM multiplexing system comprises a plurality of input buffers, each of which stores input data from a corresponding one of a plurality of input lines, and a scheduler for routing a plurality of output data from the input buffers on a single link. In this ATM multiplexing system, a proper scheduling algorithm is required to avoid a cell conflict. Also, the conventional ATM multiplexing system is complex in design and has trade-off between functions thereof.
Referring to FIG. 1B, there is shown a block diagram of another conventional ATM multiplexing system. As shown in this drawing, the conventional ATM multiplexing system. As shown in this drawing, the conventional ATM multiplexing system employs a train scheduling manner including the most basic scheduler. Each of a plurality of input buffers stores input data from a corresponding one of a plurality of input lines. An empty slot generator is provided to generate an empty slot (i.e., idle cell) at a fixed speed. The empty slot from the empty slot generator enters the processing nodes sequentially, being transferred through adjacent processing nodes. Upon the presence of a cell from one of the input buffers to be transmitted, the cell is transmitted by being placed in the empty slot. In this case, a cell transmission priority is always present in the processing node nearest to the empty slot generator, resulting in prevention of a cell conflict. However, the priority of the processing nodes is fixed and the cell transmission opportunity does not frequently occur in the processing node positioned away from the empty slot generator. This results in a cell loss and a shortage of fairness.
Referring to FIG. 1C, there is shown a block diagram of another conventional ATM multiplexing system. This ATM multiplexing system is proposed by Chao (Bellcore, U.S.A.). In order to make up for fixed priority, the Chao multiplexing system comprises a (n+1).times.(n+1) switch matrix provided at the output stages of an empty slot generator and the processing nodes of FIG. 1B, in addition to the construction of FIG. 1B. The switch is selectively connected to change the priority. However, the Chao multiplexing system does not propose a scheduling technique for reducing a cell lost rate.
Referring to FIG. 1D, there is shown a block diagram of another conventional ATM multiplexing system. This ATM multiplexing system is a dynamic ATM multiplexing system proposed by Chen (the Nationalist China). Here, the cell loss rate is reduced by reducing overflow conditions of the input buffers by applying the principle of full-buffer-first-service to the Chao system. In the case where the input buffers are full, the data transmission is performed at the next cell transmission time, so that the overflow of the buffers cannot instantaneously take place. Each of the processing nodes detects the full state of the corresponding input buffer and sends a self-node identifier to a controller upon detection of the full state. Upon receiving the self-node identifiers from the processing nodes, the controller controls the switch to connect the output of the empty slot generator to the processing node with a smallest one of the self-node identifiers.
In the above-mentioned Chao ATM multiplexing system, an input stage at a higher position has a higher priority since the processing nodes are implemented in a daisy-chain manner. Hence, the input stage at the higher position must be assigned for a better service. In this manner, the Chao ATM multiplexing system is available at a subscriber state in performing cell assembling according to a desired service and then performing cell multiplexing, but not available for the cell multiplexing in a remote node or a network termination unit. Also, int he case where burst-type traffic is applied to the input stage of a higher priority, cell loss takes place at the input state of a lower priority. This results in a shortage of fairness of the cell transmission. Also, a faulty operation of only one node results in a malfunction of the whole system. To solve this problem, the switch must be controlled to separate a processing node with a fault from others.
In the above-mentioned dynamic ATM multiplexing system, the controller sends a "reconfiguration" signal to the empty slot generator upon the change of the switch connection. At this time, the generated cell (slot) of the empty slot generator must indicate a data full state so that the cells from the processing node are prevented from being transmitted upon the change of the switch connection. For this reason, a channel capacity for the cell transmission is wasted for that period. Also, the connection reconfiguration must not be performed in the middle of a cell transmission from the processing node so that a valid cell is not subjected to a damage. On the other hand, an idle cell must continuously be transmitted for a cell synchronization when cell transmission is not performed. In this case, the cell synchronization may be lost because the transmission of the idle cell is not performed during the changing of the switch connection. Because a cross-point switch has a complex circuitry construction, there must be present at every node a function of converting the transmission cells from the input buffer into a bit stream for parallel data transmission in the unit of a byte. This results in waste of the circuitry and requires a very high switching speed.
Referring to FIG. 1E, there is shown a block diagram of another conventional ATM multiplexing system. This ATM multiplexing system is proposed by Karo (Fujitsu, Japan). The Karo ATM multiplexing system has a construction different from those mentioned above. As shown in this drawing, the cells transmitted from the plurality of subscriber lines are stored in the corresponding input buffers. A plurality of multiplexing switches are provided to concentration-multiplex the cells from the input buffers on a single transmission line. Each of a plurality of multiplexing controllers is provided to control a corresponding one of the multiplexing switches. The cells from the input buffers are concentration-multiplexed according to states of the multiplexing controllers.
A flag signal line is used to couple the multiplexing controllers in a ring-shaped structure. A flag signal FLG indicates a channel use and a multiplexed state of each input stage. The flag signal FLG is circulated along the flag signal line to assign an authority to the transmission of the cells stored in the input buffers. As seen from FIG. 1E, the multiplexing controllers are distributed, instead of using the switch in the above-mentioned basic construction, in a manner proper to the ring-shaped structure based on a topology of the subscribers.
Referring to FIG. 1F, there is shown a block diagram of another conventional ATM multiplexing system. This ATM multiplexing system is proposed by Rocha (Portugal). As shown in this drawing, the Rocha ATM multiplexing system comprises multiplexing parts, input/output data buses and a bus use arbitration bus. Each of the multiplexing parts includes an input buffer, a bus control circuit, a bus use conflict arbitration circuit and a transmission controller. For the purpose of performing a scheduling function for the multiplexing, a processor sequentially reads priority vectors through the bus use arbitration bus and uses the output data bus according to the determined priority to enable data transmission. The priority vectors have determination variables which are generated for the control of bus access by the bus use conflict arbitration circuit.
Therefore, the processor must have excellent function and speed to implement the ATM multiplexing system capable of transmitting the cells at a high speed. Also, the processor is complex in construction and is not suitable for a service with burst-type traffic, in that it checks the states of the input buffers in the daisy-chain manner using the single bus use arbitration bus. Further, in each multiplexing part, there is present a structure for generating an idle cell or an unassigned cell. At least one of the multiplexing parts must be present at an active state to generate the unassigned cell. Moreover, each multiplexing part must have a header change function. As a result, the circuitry is complex, and it is difficult to manage a link table.